The negative word line technique, in which the gate of the transfer transistor in a DRAM cell is maintained at a bias voltage below ground (V.sub.ss) is commonly used to increase retention time by reducing leakage through the transfer transistor.
When this is done, the voltage swing on the wordline driver circuit is increased, as there is now a greater voltage swing (from V.sub.ss to the boosted driver voltage V.sub.pp) than was the case when the low bias voltage is at ground, and there is greater voltage stress on the devices in the driver circuit and therefore decreased reliability.
The art has addressed this situation by placing a buffer nfet in series in the driver output stage, by increasing the thickness of the gate oxide in the driver pfet and by increasing the channel length on the devices. These approaches impose extra cost on the circuit.
In one example, shown in "Offset Word-Line Architecture for Scaling DRAMs to the Gigabit Level", in the IEEE Journal of Solid State Circuits, Vol 23, No. 1, February 1988, the authors propose a scheme for a grounded (not negative) wordline, in which the wordline driver includes a high-threshold pfet and a low-threshold nfet. The result is that the leakage current through the selected wordline is reduced, but the leakage current on all the non-selected wordlines is increased, so that the total leakage from the circuit during standby will be unacceptably high.